1. Field of the Invention
The present invention relates to a delay lock circuit. More particularly, the present invention discloses a delay lock circuit using a bisection algorithm and its related method.
2. Description of the Prior Art
Today, people are familiar with the management, delivery, and exchange of digital information. Mobile phones, personal digital assistants (PDA), information applicants (IA), and digital devices of personal computers are used to conveniently manage and deliver digital information.
When delivering, exchanging, and managing digital information, the digital device must operate according to clocks so as to handle sequential digital signals. For example, the central processing unit (CPU) of the personal computer uses clocks for each built-in digital circuit to deal with the access and management of data. Mobile phones use clocks to trigger a beginning of receiving and transmitting digital information. If a mobile phone is used as a receiver to receive digital signals, the receiving end must synchronize local clocks with clocks of the received digital signals so as to receive and transmit digital information accurately.
In the process of managing digital information, the technique of generating another synchronized clock by a reference clock is widely used. In digital circuits, we can increase or decrease one frequency of two synchronized clocks to get two harmonic clocks with different frequencies so as to handle digital information among different digital circuits conveniently. Besides, we can use one clock to generate another synchronized clock containing much more current to drive the digital circuit with more logic gates. In digital mobile communication systems, when a mobile phone is used as a receiving end to generate a synchronized clock according to the received clock, the clock of received electronic wave is weak and contains little power. At the receiving end, it is necessary to generate a stronger synchronized clock to make the mobile phone operate normally.
The circuit that generates the synchronized clock according to a reference clock is generally known as a phase lock loop circuit. One embodiment of the phase lock loop circuit is the delay lock loop (DLL) circuit. Please refer to FIG. 1, which is a functional block diagram of a known delay lock loop circuit 10. The delay lock loop circuit 10 generates the synchronized second clock 14 according to the incoming first clock 12. The delay lock loop circuit 10 comprises a delayer 16, a buffer 20, a comparator 24, and a controller 22. The delayer 16 electronically connected to the buffer 20 has a plurality of delay units 18. The output of the buffer 20 feeds back to one side of the comparator 24, and the other side of the comparator 24 receives the input from the first clock 12. The output 25 of the comparator 25 is electronically connected to the controller 22, and the controller 22 controls the delayer 16.
The operation of the delay lock loop circuit 10 is illustrated as follows. When the first clock 12 is fed into the delayer 16, the delayer 16 delays the first clock 12 by certain periods of time to generate the second clock 14. The second clock 14 generated from the delayer 16 is fed into the buffer 20, and the buffer 20 equips the second clock 14 with higher current to be outputted. In order to synchronize the second clock 14 with the first clock 12, the delay lock loop circuit 10 has one feedback mechanism for correcting clocks. In such a mechanism, the first clock 12 and the second clock 14 are fed into the comparator 24 to check whether both frequencies are the same. The result of the comparison is fed into the controller 22. According to the result of the comparison, the controller 22 uses the delay units 18 to change the delay time of the second clock 14 so as to correct the delay time between the second clock 14 and the first clock 12. Among a plurality of delay units inside the delayer 16, each of the delay units can delay the second clock 14 by a fixed unit of time. The delayer 16 activates a different amount of the delay units to change the delay time of the second clock 14.
The method for synchronizing the second clock 14 with the first clock 12 is further illustrated by the flow chart of FIG. 2. Please refer to FIG. 2, which is a flow chart of a known delay lock loop circuit 10 that changes the delay time of the second clock 14 and synchronizes the second clock 14 with the first clock 12. The process contains the following steps.
Step 26: The delay lock process begins and starts adjusting the delay time of the second clock 14 to lock and synchronize with the first clock 12. In the beginning, the controller 22 controls the delayer 16 to generate a corresponding time period of the second clock 14 after delaying a fixed interval (initial value of the delay time) according to each clock trigger generated by the first clock 12. Because the delay lock loop circuit 10 has an unknown system delay, unknown delay time between the first clock 12 and the second clock 14, and the initial value of the delay time, the second clock, therefore, can not be synchronized with the first clock.
Step 28: After the second clock 14 is generated, the first clock 12 and the second clock 14 are fed into the comparator 24 to compare the periods of the two clocks. The comparator 24 determines a relative relation between the two clocks, that is, the lead/lag relation between the period of the first clock 12 and the corresponding period of the second clock 14. After comparing, the comparator 24 transmits a corresponding comparison signal to the controller 22, and the comparison signal determines whether one period of the first clock 12 leads the corresponding period of the second clock 14. In the present step, the comparator 24 is used to compare the lead/lag relation between the first clock 12 and the second clock 14. If the first clock 12 leads, go to Step 30; else, go to Step 32.
Step 30: After receiving the comparison signal from the comparator 24, the controller 22 decides how to adjust the delay time of the second clock 14. The controller 24 activates one delay unit 18 less when preceding Step 30. As shown above, each delay unit 18 can delay the second clock 14 by a unit of time (dt). The unit of delay time, for example, could be 1 nanosecond (ns). When activating one delay unit 18 less, the delay time of the second clock 14 decreases by one unit of delay time (dt). After adjusting the delay time of the second clock 14, the process jumps to Step 28 for comparing the first clock 12 and the second clock 14 again.
Step 32: Adjust the corresponding delay time of the second clock 14 according to the comparison result obtained from Step 28. In the present step, the controller 22 controls the delayer 16 to activate one delay unit 18 more, for increasing one unit of delay time of the second clock 14. After adjusting the delay time of the second clock 14, the process jumps to Step 28 for comparing the first clock 12 and the second clock 14 again.
The following example is used to illustrate the procedure mentioned above. Please refer to FIG. 3, which is a waveform plot of the first and second clocks when a prior art delay lock loop circuit is synchronizing the first clock with the second clock. In FIG. 3, the horizontal axis represents time, and the perpendicular axis represents a magnitude of the wave. Because the time needed for the whole process of the known phase lock loop circuit is long, the waveforms of the first and second clocks are divided into three parts. Therefore, there are six waveforms in FIG. 3. The waveform 12a intersects waveform 12b at the point A1, and the waveform 14a intersects waveform 14b at the point A2. Similarly, the waveform 12b intersects waveform 12c at the point B1, and the waveform 14b intersects waveform 14c at the point B2. The waveforms 12a, 12b, and 12c intersect respectively at points A1 and B1 to form the whole waveform of the first clock 12 between time 0 and time 28T. Similarly, the waveforms 14a, 14b, and 14c are combined to represent the whole waveform of the second clock 14 between time 0 and time 28T. First, please refer to waveforms 12a and 14a in FIG. 3. The waveform 12a represents the waveform of the first clock 12 from time 0 to time 10T. The symbol T represents the interval of one period of the first clock 12 (as the interval 12p shown in the waveform 12a). In order to generate the synchronized second clock 14, the delay lock loop circuit 10 must keep the period of the first clock 12 fixed all the time. The delay lock loop circuit 10 adjusts the delay time of the second clock 14, so that the period of the corresponding waveform varies. The waveform 14a is the waveform of the second clock 14 between time 0 and time 10T.
When the delay lock loop circuit 10 starts operating, the delayer 16 generates the corresponding period of the second clock 14 after a certain delay time according to the trigger of the rising edge of the first clock 12. In the waveform 12a, the rising edge of the period 201a triggers the delayer 16 to generate the corresponding period 201b of the waveform 14a after a certain delay time. In FIG. 3, the relation between the period 201a and the corresponding triggered period 201b is illustrated by the arrow C. Similarly, the period 202a of the waveform 12a triggers the period 202b of the waveform 14a, and the period 203a of the first clock 12 triggers the period 203b of the second clock 14, etc.
After the delayer 16 generates the period 201b of the second clock 14 according to the trigger of the period 201a, the comparator 24 compares the lead/lag relation between the first clock 12 and the second clock 14. After comparing, the comparator 24 generates the comparison signal according to the relative relation between the period 201b and the period 202a. In other words, when comparing the second clock 14 with the first clock 12, the comparator 24 uses the period 202a which lags behind the period 201a by one period (1T) as a reference period to compare with the period 201b of the second clock 14. Then, the comparator 24 determines whether the second clock 14 is synchronized with the first clock 12. Taking FIG. 3 for example, the comparator 24 judges that the first clock 12 leads the second clock 14 because the period 201b of the first clock 12 lags behind the period 202a of the first clock 12. As mentioned above, the delayer 16 generates the period 201b of the second clock 14 according to the trigger of the period 201a of the first clock 12. There is a critical delay between the period 201a and the period 201b because of the unknown system delay and the initial value of the delay time of the delayer 16, and it is impossible for the period 201b to be synchronized with the period 202a in the beginning. As shown in FIG. 3, there is an interval (indicated by the arrow 15a)of 25 dt between respective rising edges of the period 202a and the period 201b. Please note that the comparator 24 only indicates the lead/lag relation between the period 202a and the period 201b. The comparator 24 does not measure the delay time, that is, the interval between respective rising edges of two periods.
After comparing the period 202a with the period 201b, the comparator 24 judges that the second clock 14 lags behind the first clock 12. The controller 22, therefore, controls the delayer 16 to activate one delay unit 18 less for decreasing the delay time by 1 dt (Step 30). When the delayer 16 starts generating the corresponding period 202b by the trigger of the rising edge of the period 202a, the delay time between the period 202a and the period 202b decreases by 1 dt because one delay unit 18 less is used. Similarly, the interval between the period 202b and the reference period 203a decreases by 1 dt to 24 dt(as shown in FIG. 3). Certainly, the comparator 24 compares the period 203a with the period 202b again (Step 28). If the first clock 12 still leads the second clock 14, the controller 24 controls the delayer 16 to active one delay unit 18 less again (Step 30). Then, the delayer 16 generates the period 203b by the trigger of the period 203a of the first clock 12. The interval between the two periods 203a and 203b decreases by 1 dt again because of one delay unit 18 less being used. Therefore, the interval between the rising edges of the reference period 204a and the period 203b decreases by 1 dt to 23 dt.
With the comparison and adjustment of the known delay lock loop circuit 10, the interval between the reference period and the period of the second clock 14 continuously decreases by increments of 1 dt. The prior art delay lock loop circuit 10 repeatedly uses a fixed interval (1 dt) for adjusting each period of the second clock 14. As shown in FIG. 3, when the delayer 16 uses the trigger of the period 210a to generate the corresponding period 210b, the interval between respective rising edges of the period 210b and the reference period 211a decreases to 16 dt (please refer to waveforms 12b and 14b). When the time reaches 20T (please refer to waveforms 12c and 14c), the interval between period 220b and the corresponding reference period 221a has decreased to 6 dt. When the time reaches 26T, the interval between the period 226b and the corresponding reference period 226a exactly equals one period (1T) of the first clock 12. Meanwhile, the period 226b of the second clock is synchronized with the period 227a. After repeatedly adjusting, the delayer 12 activates a reasonable amount of delay units 18 to make the interval between respective rising edges of the period of the first clock 12 and the triggered period of the second clock 14 equal one period (1T) of the first clock 12. As mentioned above, the delayer 16 uses the rising edge of the first clock 12 to trigger the corresponding rising edge of the second clock 14, but there is a delay time because of the unknown system delay and different amounts of delay units 18 activated by the delayer 16. In the beginning, the delayer 16 does not obtain the exact value of system delay. Similarly, the amount of delay units used is an uncertain value. The first clock, therefore, is not synchronized with the second clock. In the following correcting process, the delay lock loop circuit 10 repeats Step 28 and Step 30 (or Step 32) to continuously adjust the delay time between the first clock and the second clock. The delay time generated from the delay units 18 activated by the delayer 16 and the unknown system delay exactly equals one period of the first clock. Now the delayer 16 generates the second clock from the trigger of the first clock, and then the second clock is synchronized with the first clock. The delay lock loop circuit 10 repeatedly performs the correcting process to correct the errors generated from the system disturbance. But, the delayer 16 only increases or decreases one or two delay units activated for slightly correcting the disturbance generated from the system.
The disadvantage of the prior art technique is that it spends a longer time on synchronizing the second clock with the first clock because the known technique adjusts by one unit time (1 dt) each cycle. In order to increase the accuracy for the second clock to lock the first clock, the unit of delay time must be short enough to prevent quantization errors. Taking FIG. 3 for example, if the delay time between the period of the first clock and the corresponding period of the second clock is 0.5 dt, the second clock can not be synchronized with the first clock however the delay lock loop circuit adjusts. Because the delay lock loop circuit uses the unit of delay time (dt) as the minimum unit to correct the delay time of the second clock, the interval less than one unit of delay time becomes a quantization error. It is impossible to correct such a quantization error. In other words, the length of the unit delay time can be used to measure the quantization error.
In order to decrease the quantization errors, when designing the digital delay lock loop circuit such as the delay lock loop circuit 10, it is necessary to reduce the unit of delay time (dt) as much as possible. For example, if one period T of the first clock in FIG. 3 equals 100 dt (1 dt=T/100), the quantization error which makes the first clock unable to be synchronized with the second clock is less than 0.01T. If the unit of delay time dt reduces to 0.001T, the quantization error is less than 0.001T. The smaller the unit of delay time, the more cycles needed to adjust the delay time of the second clock. As shown in FIG. 3, the known technique only adjusts (increases or decreases) one unit time each period T when adjusting the delay time of the second clock. The smaller the unit of delay time is, the smaller amount of adjustment is applied in one period T. On the contrary, it spends a long time on completing the whole correcting process. In other words, it needs more periods T to adjust the second clock for being synchronized with the first clock. Of course, a delay lock loop circuit must not only provide a small quantization error, but must also quickly synchronize the first clock with the second clock.